Most complex electronic circuits operate in synchronous mode and require an oscillating clock signal to synchronize various actions throughout the circuit. The design and placement of clock generation and distribution circuitry is particularly sensitive because a clock signal is delayed as it passes through buffers and along lengthy conductive routes. The likelihood of errors or faults during operation of the circuit can increase as uncompensated delay in a clock signal increases, particularly when moving between different clock domains. For example, when communicating with off-chip interfaces, the insertion delay of the on-chip clock distribution tree should be compensated for to prevent phase errors between the on-chip clock and the off-chip clock at the interface. Conventional phase-locked loops (PLLS) may be used to adjust the phase of clock signals by placing the entire clock tree in the feedback loop to the PLL. However, long feedback loops may tend to make the PLL unstable or introduce a lengthy settling time after adjustment. Testing of the electronic circuit is also complicated by analog phase-locked loops because it can be difficult to introduce phase errors to determine the operating margins of the circuit.